1. Technical Field
The present invention relates to a video disk player for playing a disk on which a video signal is recorded.
2. Technical Background
When a plurality of video signal picture images provided by a plurality of video disk players are synthesized by a plurality of display devices, it is necessary to perform a so-called external synchronization such that the plurality of, video disk players play the disk in synchronization with the same external synchronization signal. FIG. 3 shows a conventional video disk player for enabling such an external synchronization.
In the video disk player 10 shown in FIG. 3, disk 1 is driven and rotated by spindle motor 2. A signal recorded on disk 1 is read by pickup 3 through the rotation of disk 1. An RF (high frequency) signal output from pickup 3 is amplified by RF amplifier 4 and supplied to FM-demodulating circuit 5 to reproduce a video signal. As is well known, the player comprises a focus servo loop for converging a light beam emitted from pickup 3 onto a recording face of disk 1 and to form a light spot for reading information, and a tracking servo loop for causing the light spot to accurately follow a recording track of disk 1, etc. although these servo loops are not shown in FIG. 3.
The read video signal outputted from FM-demodulating circuit 5 is supplied to one input terminal of changeover switch 6 and synchronization separating circuit 7. A horizontal synchronization signal is separated by synchronization separating circuit 7 from the read video signal and is supplied to spindle servo circuit 8. Spindle servo circuit 8 is constructed such that spindle motor 2 is driven in accordance with the difference in phase between a reproduced horizontal synchronization signal and a reference horizontal synchronization signal described later.
An external reference composite synchronization signal is generated by circuit g and supplied through an input terminal of video disk player 10 to circuit 11 for generating the external reference horizontal synchronization signal, circuit 12 for generating a reference frame pulse, and circuit 13 for detecting an external input. Reference frame pulse generating circuit 12 is constructed to output the reference frame pulse generated once every frame period in synchronization with the beginning of each frame defined by the external reference composite synchronization signal. The output of reference frame pulse generating circuit 12 is supplied to phase comparing circuit 14 and is compared in phase with a reproduced frame pulse outputted from reproducing frame pulse generating-circuit 15.
Reproducing frame pulse generating circuit 15 is constructed to output the reproducing frame pulse generated once every frame period in synchronization with the beginning of each frame of the read video signal as defined by a vertical synchronization signal and an equivalent pulse in the reproduced composite synchronization signal separated from the read video signal by synchronization separating circuit 7, for example. Phase comparing circuit 14 produces a difference signal in accordance with the difference in phase between the reference and reproduced frame pulses. This difference signal is inputted as a control signal to VCO (voltage control-type oscillator) 16. VCO 16 is constructed such that a self-scanning frequency is approximately equal to a horizontal synchronization frequency. An oscillating frequency of this VCO 16 is changed in accordance with the difference signal from phase comparing circuit 14 with the horizontal synchronization frequency as a center. The output of VCO 16 is supplied to one input terminal of change-over switch 17.
The external reference horizontal synchronization signal is separated from the external reference composite synchronization signal by external reference horizontal synchronization signal generating circuit 11 and is supplied to the other input terminal of change-over switch 17. An output of lock detecting circuit 18 is supplied as a switch control signal to change-over switch 17. Lock detecting circuit 18 is constructed to output a lock detecting signal when the level in voltage of the difference signal outputted from phase comparing circuit 14 is less than a predetermined value. Change-over switch 17 selectively outputs the external reference horizontal synchronization signal when the lock detecting signal is provided, and selectively outputs the output of VCO 16 when the lock detecting signal is not provided.
The output of change-over switch 17 is supplied to one input terminal of change-over switch 19. An internal reference horizontal synchronization signal outputted from frequency divider 21 is supplied to the other input terminal of change-over switch 19. Frequency divider 21 divides the frequency of a signal having frequency 4f.sub.sc (four times a color subcarrier frequency) outputted from oscillator 22 and produces the internal reference horizontal synchronization signal having a frequency equal to that of the horizontal synchronization signal. An output of external input detecting circuit 13 is supplied as a control signal to change-over switch 19. External input detecting circuit 13 detects that the external reference composite synchronization signal is supplied by detecting the interval of an input pulse by e.g., a monostable multivibrator, etc., and generates an external input detecting signal. Change-over switch 19 selectively outputs the output of change-over 17 when the external input detecting signal is provided, and selectively outputs the internal reference horizontal synchronization signal as an output of frequency divider 21 when the external input detecting signal is not provided.
The output of change-over switch 19 is supplied to spindle servo circuit 8 as a reference horizontal synchronization signal. The output of oscillator 22 is supplied to background or back video generating circuit 23. Background video generating circuit 23 controls the operation of a character generator, etc., by the output of oscillator 22 for example, and generates a background video signal corresponding to a predetermined image. The output of background video generating circuit 23 is supplied to the other input terminal of change-over switch 6. A squelch command signal outputted from squelch command signal generating circuit 24 is supplied to a control input terminal of change-over switch 6. Squelch command signal generating circuit 24 generates the squelch command signal when servo loops of e.g., a focus servo loop, etc., attain a non-lock state. Change-over switch 6 selectively outputs a read video signal outputted from FM-demodulating circuit 5 when the squelch command signal is not provided, and selectively outputs the background video signal outputted from background video generating circuit 23 when the squelch command signal is provided.
In the above-mentioned construction, when the external reference composite synchronization signal is not provided from external reference composite synchronization signal generating circuit 9, the external input detecting signal is not outputted from external input detecting circuit 13, and the internal reference horizontal synchronization signal outputted from frequency divider 21 is selectively outputted from change-over switch 19. When this internal reference horizontal synchronization signal is supplied to spindle servo circuit 8, the rotary speed of spindle motor 2 is controlled such that the phase of the horizontal synchronization signal in the read video signal is in conformity with the phase of the internal reference horizontal synchronization signal, thereby performing a control with respect to the time axis of the read video signal.
When the external reference composite synchronization signal is supplied from external reference composite synchronization signal generating circuit 9, the external input detecting signal is outputted from external input detecting circuit 13 and is supplied to change-over switch 19. Thus, the output of change-over switch 17 is selectively outputted from change-over switch 19. At this time, when the lock detecting signal is not outputted from lock detecting circuit 18, the output of VCO 16 is selectively outputted from change-over switch 17. VCO 16 is oscillated at a frequency in accordance with the difference in phase between the reference frame pulse and the reproduced frame pulse. The output of VCO 16 is supplied to spindle servo circuit 8 as the reference horizontal synchronization signal so that the rotary speed of spindle motor 2 is accelerated and decelerated in accordance with the phase difference between the reference and reproduced frame pulses. When the reproduced frame pulses are in advance of the reference frame pulses, the oscillating frequency of VCO 16 is lowered and a loop delaying the reproduced frame pulses is formed so that both frame phases are changed so as to be in conformity with each other. As a result, first and second fields of the reproduced composite synchronization signal and vertical synchronization signal are in conformity with the external reference composite synchronization signal. At this time, when the phase difference of both frames becomes less then a predetermined value (e.g., 0.5 H), the lock detecting signal is outputted from lock detecting circuit 18 and the output of external reference horizontal synchronization signal generating circuit 11, i.e., the stable external reference horizontal signal, is selectively outputted from change-over switch 17, thereby completing the external synchronization.
In the conventional apparatus mentioned above, change-over switch 19 is connected between frequency divider 21 and spindle servo circuit 8. This makes it impossible to use an integrated circuit with the spindle servo circuit 8 and frequency divider 21 formed on a single chip, whereby the reference horizontal synchronization signal could be internally produced. Further, oscillator 22 is different from a reference oscillator for generating the external reference composite synchronization signal in external reference composite synchronization signal generating circuit 9. Therefore, the timing of the vertical synchronization signal is shifted when the read video signal and the background video signal are switched by change-over switch 6, thereby disturbing a reproduced image.